FED-Shop
FED-Dokumente und IPC-Richtlinien zu Design, Leiterplatten- und Baugruppen-Fertigung jederzeit bequem bestellen.
J-STD-001JS (Hardcopy)
IPC-J-STD-001 - Revision J - Addendum - Space and Military: Space and Military Applications Electronic Hardware Addendum to IPC J-STD-001J Requirements for Soldered Electrical and Electronic Assemblies
English. 28 pages. Released: 01.01.2025.
IPC J-STD-001JS Space and Military Addendum supplements or replaces specifically identified requirements of IPC J-STD-001J requirements for soldered electrical and electronic assemblies that must survive the vibration and thermal cyclic environments of getting to and operating in space and military applications.
J-STD-003C-WAM1&2 (Hardcopy)
Solderability Tests for Printed Boards
Englisch. Stand: Oktober 2012, 27 Seiten
J-STD-003C prescribes test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands and plated-through holes utilizing either tin-lead or lead-free solders. This standard is intended for use by both vendor and user. The objective of the solderability test methods described in this standard is to determine the ability of printed board surface conductors, attachment lands and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes. This standard describes test methods by which both surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability.
Revision "C" contains the latest information about gauge repeatability and reproducibility (GR&R) of solderability tests as well as updated illustrations.
J-STD-003C-WAM1&2 (PDF)
Solderability Tests for Printed Boards
Englisch. Stand:2014, 27 Seiten. Keine Druckberechtigung, DRM-Schutz, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
J-STD-003C prescribes test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands and plated-through holes utilizing either tin-lead or lead-free solders. This standard is intended for use by both vendor and user. The objective of the solderability test methods described in this standard is to determine the ability of printed board surface conductors, attachment lands and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes. This standard describes test methods by which both surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability.
Revision "C" contains the latest information about gauge repeatability and reproducibility (GR&R) of solderability tests as well as updated illustrations.
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
J-STD-003D (Hardcopy)
Solderability Tests for Printed Boards
Englisch. Stand: Januar 2023, 44 Seiten
The IPC J-STD-003D standard describes solderability determinations that are made to verify that the printed board fabrication processes and subsequent storage have had no adverse effect on the solderability of those portions of the printed board intended to be soldered. Solderability is determined by evaluation of a test specimen which has been processed as part of a panel of boards and subsequently removed for testing per the method selected. IPC J-STD-003D provides solderability test methods to determine the acceptance of printed board surface conductors, attachment lands, and plated-through holes to wet easily with solder, and to withstand the rigors of the printed board assembly processes.
J-STD-003D (PDF) Single User
Solderability Tests for Printed Boards
Englisch. Stand: Januar 2023, 44 Seiten.
The IPC J-STD-003D standard describes solderability determinations that are made to verify that the printed board fabrication processes and subsequent storage have had no adverse effect on the solderability of those portions of the printed board intended to be soldered. Solderability is determined by evaluation of a test specimen which has been processed as part of a panel of boards and subsequently removed for testing per the method selected. IPC J-STD-003D provides solderability test methods to determine the acceptance of printed board surface conductors, attachment lands, and plated-through holes to wet easily with solder, and to withstand the rigors of the printed board assembly processes.
J-STD-004B w/Amend 1 (PDF) Single User
Requirements for Soldering Fluxes
Englisch. 20 pages. Stand: November 2011; inkl. Amendment 1; Keine Druckberechtigung, DRM-Schutz, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This standard prescribes general requirements for the classification and characterization of fluxes for high quality solder interconnections. This standard may be used for quality control and procurement purposes. The purpose of this standard is to c lassify and characterize tin/lead and lead-free soldering flux materials for use in electronic metallurgical interconnections for printed circuit board assembly. Soldering flux materials include the following: liquid flux, paste flux, solder paste, s older cream, and flux-coated and flux-cored solder wires and preforms. It is not the intent of this standard to exclude any acceptable flux or soldering material; however, these materials must produce the desired electrical and metallurgical intercon nection. 20 pages. Released December 2008.
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
J-STD-004C (Hardcopy)
Requirements for Soldering Fluxes
Englisch. 32 pages. Stand: Januar 2022
The IPC J-STD-004C standard prescribes general requirements for the classification and characterization of fluxes for high quality solder interconnections. The IPC J-004C standard may be used for quality control and procurement purposes.
J-STD-004C (PDF) Single User
Requirements for Soldering Fluxes
Englisch. 32 pages. Stand: Januar 2022
The IPC J-STD-004C standard prescribes general requirements for the classification and characterization of fluxes for high quality solder interconnections. The IPC J-004C standard may be used for quality control and procurement purposes.
J-STD-005A (PDF) Single User
Requirements for Soldering Pastes
Englisch. 10 pages. Stand: Februar. Keine Druckberechtigung, DRM-geschützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This standard lists requirements for qualification and characterization of solder paste. It references test methods and criteria for metal content, viscosity, slump, solder ball,tack and wetting of solder pastes. Additional support is provided in IPC-HDBK-005, Guide to Solder Paste Assessment (not included with purchase of this standard). Supersedes J-STD-005. 10 pages.Released February 2012.
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
J-STD-006C (PDF) Single User
Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders
Englisch. 22 pages. Stand: July 2013. Keine Druckberechtigung, DRM-Schutz, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This standard prescribes the nomenclature, requirements and test methods for electronic grade solder alloys; for fluxed and non-fluxed bar, ribbon and powder solders for electronic soldering applications; and for ++special++ electronic grade solders. This is a quality control standard and is not intended to relate directly to the material+s performance in the manufacturing process. Solders for applications other than electronics should be procured using ASTM B-32. This standard is one of a set of three joint industry standards that prescribe the requirements and test methods for soldering materials to be used in the electronics industry. The other two standards in this set are IPC/EIA J-STD-004, Requirements for Soldering Fluxes, and IPC/EIA J-STD-005, Requirements for Soldering Pastes.
This "C" revision has been updated to address intentional additions to a solder alloy and impurities in the alloy. In addition, the tables and appendices have been.
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
J-STD-006C-AM1 (PDF) Single User english
Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications - Amendment 1
Englisch. 12 pages. Stand: November 2017. Keine Druckberechtigung. DRM-Schutz, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
The J-STD-006C-AM1 amendment provides better detail of a solder alloy's maximum allowed deviation about the nominal level of the element's mass than was provided in past alloy standards. The J-STD-006C-AM1 amendment provides information on negative effects of adding rare earth elements to specific, heavy tin- containing, lead-free solder alloys and propensity of tin whisker formation. Finally, the J-STD-006C-AM1 amendment inserted five new, patented lead-free solder alloys from 3 separate alloy suppliers for users of the J-STD-006C standard.
Single-Device DRM-Protected Document
This document has single-device/user digital rights management (DRM) protection. This document will only be accessible by a single user on a single device. If you are purchasing this DRM-protected document for another user, you will need to provide contact information for that user when placing your order.
J-STD-006C-AM1 Hardcopy
Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications - Amendment 1
Englisch. 12 pages. Stand: November 2017.
The J-STD-006C-AM1 amendment provides better detail of a solder alloy's maximum allowed deviation about the nominal level of the element's mass than was provided in past alloy standards. The J-STD-006C-AM1 amendment provides information on negative effects of adding rare earth elements to specific, heavy tin- containing, lead-free solder alloys and propensity of tin whisker formation. Finally, the J-STD-006C-AM1 amendment inserted five new, patented lead-free solder alloys from 3 separate alloy suppliers for users of the J-STD-006C standard.
Single-Device DRM-Protected Document
This document has single-device/user digital rights management (DRM) protection. This document will only be accessible by a single user on a single device. If you are purchasing this DRM-protected document for another user, you will need to provide contact information for that user when placing your order.
J-STD-020D-DE Papierversion
Klassifizierung feuchtigkeits-/reflowempfindlicher nichthermischer Halbleiterbauteile für Oberflächenmontage
Deutsch. 13 Seiten. Juli 2007
Das Dokument enthält auf 13 Seiten A4 Verfahren zur Feststellung der Sensibilität nicht hermetischer SMD-Halbleiterbauteile gegenüber durch Feuchtigkeit verursachtem Bauteilstress. Im Ergebnis dessen werden die Bauteile in entsprechende MSL-Klassen (Moisture Sensitivity Level) eingestuft, so dass richtige Handhabung und Verpackung sowie geeigneter Versand und Einsatz vollzogen werden können. J-STD-020D ist eng mit IPC/JEDEC J-STD-033B.1 verbunden.
J-STD-020F (Hardcopy)
IPC/JEDEC-J-STD-020 - Revision F: Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)
Englisch. Stand: 2022. Seiten: 30.
IPC/JEDEC J-STD-020F standard is to identify the classification level of nonhermetic SMDs designed for surface mount assembly that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. IPC/JEDEC J-STD-020F standard may be used to determine what classification level should be used for nonhermetic SMD qualification. Passing the criteria in this test method is not sufficient by itself to provide assurance of long-term reliability. The Moisture Sensitivity Levels (MSLs) rating generated for an SMD by this document is utilized to determine the soak conditions for preconditioning as per JESD22-A113 and how the SMD can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations as per J-STD-033. For IC devices that may be process sensitive, please refer to J-STD-075 to determine if a PSL (Process Sensitivity Level) classification is required.
J-STD-020F (PDF) Single User
IPC/JEDEC-J-STD-020 - Revision F: Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)
Englisch. 30 Seiten. Stand: 2022
IPC/JEDEC J-STD-020F standard is to identify the classification level of nonhermetic SMDs designed for surface mount assembly that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. IPC/JEDEC J-STD-020F standard may be used to determine what classification level should be used for nonhermetic SMD qualification. Passing the criteria in this test method is not sufficient by itself to provide assurance of long-term reliability. The Moisture Sensitivity Levels (MSLs) rating generated for an SMD by this document is utilized to determine the soak conditions for preconditioning as per JESD22-A113 and how the SMD can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations as per J-STD-033. For IC devices that may be process sensitive, please refer to J-STD-075 to determine if a PSL (Process Sensitivity Level) classification is required.
J-STD-026 (PDF) Single User
Semiconductor Design Standard for Flip Chip Applications
Englisch. 43 pages. Stand: August 1999. Keine Druckberechtigung, DRM-schützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This standard addresses semiconductor flip chip design requirements. Provides information for using standard semiconductor substrates, materials, assembly and test methods with established fabrication, bumping, test and handling practices. Electrical , thermal and mechanical chip design parameters and methodologies are covered in the standard, as well as the reliability aspects associated with these conditions and processes. The information applies to all new designs as well as modifications of n on-flip chip designs. Developed by IPC and EIA. 43 Pages.
J-STD-027 (PDF) Single User
Mechanical Outline Standard for Flip Chip and Chip Size Configurations
Englisch. 13 pages. Stand: Februar 2003. Keine Druckberechtigung, DRM-geschützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This standard establishes mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface, die terminals, and interconnection balls/bumps/lands to the next level. 13 Pages.
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
J-STD-030A (PDF) Single User
Guideline for Selection and Application of Underfill Material for Flip Chip and Other Micropackages
Englisch. 32 pages. Stand: February 2014. Keine Druckberechtigung DRM-geschützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This document provides users of underfill material with guidance in selecting and evaluating underfill material. Underfill material is used to increase reliability of electronic devices by two methods: alleviate CTE mismatch (between the electronic p ackage and the assembly substrate) and/or increase mechanical strength. Materials used in underfill applications should not adversely affect device reliability (e.g. ionic impurities, alpha emitters) nor degrade electrical performance. When correctly selected and applied, underfill material should increase the life of the assembled solder joints. The following three types of currently available, underfill materials addressed in this document are: Capillary Flow Underfill, No-Flow/fluxing Underfi ll and Removable/Reworkable Underfill. 32 pages. Released February 2019
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
J-STD-032 (Hardcopy)
Performance Standard for Ball Grid Array Balls
Englisch. 10 pages. Stand: Juni 2002
This standard, developed jointly by IPC and the Electronic Industries Association (EIA) establishes the construction detail requirements for balls and other terminal structures on Ball Grid Array (BGA) packages. It also establishes a set of designati ons and expectations for product performance. A large variety of terminal structures are recognized for a wide range of applications ranging from highest reliability computer, space and military applications to disposable commodity applications.
J-STD-032 (PDF) Single User
Performance Standard for Ball Grid Array Balls
Englisch. 10 pages. Stand: Juni 2002. Keine Druckberechtigung, DRM-geschützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)
This standard, developed jointly by IPC and the Electronic Industries Association (EIA) establishes the construction detail requirements for balls and other terminal structures on Ball Grid Array (BGA) packages. It also establishes a set of designati ons and expectations for product performance. A large variety of terminal structures are recognized for a wide range of applications ranging from highest reliability computer, space and military applications to disposable commodity applications.
PDF-Datei ist DRM geschützt (rechnergebunden)! Bitte nennen Sie beim Kauf den vollständigen Namen und die E-Mailadresse des Users.
