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Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders

Englisch. 22 pages. Stand: July 2013. Keine Druckberechtigung, DRM-Schutz, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)

This standard prescribes the nomenclature, requirements and test methods for electronic grade solder alloys; for fluxed and non-fluxed bar, ribbon and powder solders for electronic soldering applications; and for ++special++ electronic grade solders. This is a quality control standard and is not intended to relate directly to the material+s performance in the manufacturing process. Solders for applications other than electronics should be procured using ASTM B-32. This standard is one of a set of three joint industry standards that prescribe the requirements and test methods for soldering materials to be used in the electronics industry. The other two standards in this set are IPC/EIA J-STD-004, Requirements for Soldering Fluxes, and IPC/EIA J-STD-005, Requirements for Soldering Pastes.

This "C" revision has been updated to address intentional additions to a solder alloy and impurities in the alloy. In addition, the tables and appendices have been.
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Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications - Amendment 1

Englisch. 12 pages. Stand: November 2017. Keine Druckberechtigung. DRM-Schutz, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)

The J-STD-006C-AM1 amendment provides better detail of a solder alloy's maximum allowed deviation about the nominal level of the element's mass than was provided in past alloy standards. The J-STD-006C-AM1 amendment provides information on negative effects of adding rare earth elements to specific, heavy tin- containing, lead-free solder alloys and propensity of tin whisker formation. Finally, the J-STD-006C-AM1 amendment inserted five new, patented lead-free solder alloys from 3 separate alloy suppliers for users of the J-STD-006C standard.

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IPC/JEDEC-J-STD-020 - Revision E: Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

Englisch. Stand: 2015. Keine Druckberechtigung, DRM-geschützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)

IPC JEDEC J-STD-020 is used to determine what moisture-sensitivity-level (MSL) classification level should be used so that surface mount devices (SMDs) can be properly packaged, stored and handled to avoid subsequent thermal and mechanical damage during the assembly solder reflow attachment and/or repair operation. J-STD-020 covers components to be processed at higher temperatures for lead-free and lower temperature Sn-Pb assemblies.

In this revision, clarification was added in numerous areas to ensure consistency in scope and application. The standard incorporates considerations for bare-die with polymer and non-IC package usage. Revision E also clarifies/updates Classification Temperature (Tc), package volume, dry weight characterization, and recording with suggested intervals during dry weight determination. Guidance on bake time is also provided in the case that bake test interruption is observed.
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IPC/JEDEC-J-STD-020 - Revision F: Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

Englisch. 30 Seiten. Stand: 2022

IPC/JEDEC J-STD-020F standard is to identify the classification level of nonhermetic SMDs designed for surface mount assembly that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. IPC/JEDEC J-STD-020F standard may be used to determine what classification level should be used for nonhermetic SMD qualification. Passing the criteria in this test method is not sufficient by itself to provide assurance of long-term reliability. The Moisture Sensitivity Levels (MSLs) rating generated for an SMD by this document is utilized to determine the soak conditions for preconditioning as per JESD22-A113 and how the SMD can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations as per J-STD-033. For IC devices that may be process sensitive, please refer to J-STD-075 to determine if a PSL (Process Sensitivity Level) classification is required.

Semiconductor Design Standard for Flip Chip Applications

Englisch. 43 pages. Stand: August 1999. Keine Druckberechtigung, DRM-schützt, !!!ACHTUNG!!! NENNEN SIE BEI DER BESTELLUNG DEN USER (NAME+E-MAIL)

This standard addresses semiconductor flip chip design requirements. Provides information for using standard semiconductor substrates, materials, assembly and test methods with established fabrication, bumping, test and handling practices. Electrical , thermal and mechanical chip design parameters and methodologies are covered in the standard, as well as the reliability aspects associated with these conditions and processes. The information applies to all new designs as well as modifications of n on-flip chip designs. Developed by IPC and EIA. 43 Pages.