FED-Shop

Statistical Process Control (SPC) Quality Rating

Englisch. 41 pages. Stand: September 2002

This document is a tool for a customer or supplier organization's internal audit group to assess a statistical process control (SPC) system against the requirements of IPC-9191. This document should be used by customers and suppliers of any size and for any commodity. This tool can be used to perform an assessment of the use of SPC at both organizational and process levels. The questions in this evaluation form are based on the guidelines for SPC implementation given in IPC-9191, which, in turn, was developed to reflect the principals of SPC represented by the International Organization for Standardization (ISO) Statistical Methods Technical Committee's document: ISO 11462-1.

This document should be used by trained evaluators, who should have a fundamental understanding of statistics and their application in manufacturing. This audit tool should be scaled to each organization's unique situation and resources.

Contained within the document are instructions for obtaining the tabula r portions of this document (sections 4 through 6) in Word Template format for electronically recording information gained during the audit process. 41 pages.

Qualifikation und Leistungsspezifikation für flexible Leiterplatten

Deutsch. Stand: Januar 2009. 43 Seiten

Die IPC-6013B (Qualifikation und Leistungsspezifikation für flexible Leiterplatten) ist in deutscher Übersetzung erhältlich. Sie enthält umfangreiches Bildmaterial und Tabellen und unter anderem die aktualisierten Anforderungen für die Metallisierung von Oberflächen, Fleckenbildung (Measling), Fremdeinschlüsse, Kleberaustritt, gefüllte durchkontaktierte Löcher und lötbarer Restring für flexible und starrflexible Leiterplatten. Die Revision vom Januar 2009 ersetzt die IPC-6013A, inklusive Amendme nt 2 und hat einen Umfang von 43 Seiten.

Beispiele
- Fremdeinschlüsse zwischen der flexiblen Leiterplatte und der Versteifung
- Gewebefreilegung (ist für die Klasse 3 nicht mehr zulässig)
- Tabelle für die Grenzwerte der Lot-Dochteffekt/Metalli sierungs-Unterwanderung. Die Grenzwerte für die Leistungsklassen (Klasse 1, 2 und 3) wurden neu spezifiziert)
- Verbindung der Versteifung. Detaillierte Spezifikation und Festlegung von Grenzwerten.
- Schulterzugang des lötfähigen Restrings
- Fehl endes Material oder Lücken beim Kleberaustritt an den Kanten der Decklage
- Messung der Schulter-Metallisierung von gefüllten, durchmetallisierten Löchern
- Füllmaterial für Sacklöcher und nicht durchgehende Verbindungslöcher. Angaben zu Grenzwerte n für die Klassen 1-3

Guidelines for OEMs in Determining Acceptable Levels of Cleanliness of Unpopulated Printed Boards

Englisch. 15 pages. Released June 2007.

Every electronics manufacturer, whether an original equipment manufacturer (OEM) or electronics manufacturing services (EMS) company, must determine if the unpopulated printed boards entering the assembly process have an adequate level of cleanliness . The question of -how clean is clean enough?- is one that has no definitive answer, as there is no 'golden number' for board cleanliness. The issue is a very complex topic, with many critical considerations, and so a single methodology to determine acceptability does not exist. Recognizing this, IPC-5702 has been written to give the printed board or printed board assembly professional some guidance on how to correlate cleanliness related data to electrical function and determine -acceptable- cl eanliness levels.

Specification for Process Carriers Used to Handle Optical Fibers in Manufacturing

Englisch. 15 pages. Released April 2003.

The purpose of this specification is to define standard practices for handling various kinds of optical fiber and to define the specifications and guidelines to be used in the design of carriers for these fibers in component manufacturing. This docum ent is identified in the overarching IPC-0040, Optoelectronic Assembly and Packaging Technology. This standard does not define a particular carrier design, but does define enough parameters to facilitate the use of fiber carriers in optoelectronic co mponent manufacturing, particularly in automated or semi-automated processes.

Standard for Determining Current Carrying Capacity in Printed Board Design

Englisch. 97 pages. Released September 2009

The sole industry standard for determining appropriate internal and external conductor sizes on printed boards as a function of the current carrying capacity required and the acceptable conductor temperature rise. This document provides guidance on h ow thermal conductivity, vias, copper planes, power dissipation and printed board material and thickness all factor into the relationship between current, conductor size, and temperature.

Generic Requirements for Electronic Product Documentation

Englisch. 26 Seiten. März 2010.

This standard establishes the generic requirements for a document set describing electronic products, and the methodology used for revision control and configuration management of the information. The generic descriptions apply to the entire document set and are used to define and maintain the electronic product. The methodology permits different grades of completeness of the documentation, as well as identifying the various products, packaging and interconnection techniques for which unambiguou s documentation is required. The requirements pertain to both hard copy and electronic data descriptions.

Sectional Requirements for Electronic Diagramming Documentation (Schematic and Logic Descriptions)

Englisch. 26 Seiten. März 2010.

This standard establishes the requirements for the documentation of electronic diagrams used as the foundation for defining the electrical interconnectivity of electronic products. The description pertains to either schematic diagrams, logic diagrams or Boolean truth tables and includes methodology for defining circuit flow, electrical or functional restrictions, or maintenance test procedures used to design or maintain the electronic product. The requirements pertain to hard copy, electronic co py or electronic data descriptions.

Sectional Requirements for Electronic Diagramming Symbol Generation Methodology

Englisch. 31 Seiten. März 2010.

This standard establishes the requirements for generation of electronic symbols used in the documentation of electronic diagrams that define the electrical interconnectivity of electronic products. The descriptions pertain to schematic symbols, logic symbols or Boolean truth tables required to define the circuit configuration. Where appropriate, the standard also includes methodology for defining circuit flow, electrical or functional restrictions, or maintenance test procedures used to design o r maintain the electronic product. The requirements pertain to both hard copy and electronic data descriptions. 31 pages.

Test Methods for Characterization of Printed Board Assembly Pad Cratering

Englisch, 17 Seiten, Dezember 2010

Mechanical bend and shock tests are routinely performed on SMT assemblies to ensure that they can sustain anticipated production, handling and end use conditions. The strains and strain rates applied to SMT assemblies during bend and shock testing can lead to a variety of failure modes in the vicinity of the solder joints. This document provides test methods to evaluate the susceptibility of printed board assembly (PBA) materials and designs to cohesive dielectric failure underneath surface mount technology (SMT) attach pads. The test methods, which include pin-pull, ball-pull, and ball shear, can be used to rank order and compare different printed board materials and design parameters.

Spherical Bend Test Method for Characterization of Board Level Interconnects

Englisch, 15 Seiten, Release 2011

This standard on spherical transient bend testing is intended to characterize the maximum allowable strain that a surface mount component's board level interconnects can withstand in flexural loading. Whereas four-point monotonic bend test methods only address simple planar bending, spherical bend tests establish strain limits of board level interconnects under worst-case flexure conditions that can occur during conventional printed board/system assembly, manufacturing and test operations. This method is applicable to surface mounted BGA components larger than 15.0 mm on a side with organically based substrates, attached to printed boards using conventional solder reflow technologies. This document was developed cooperatively with JEDEC.

Material and Process Characterization/Qualification Test Protocol for Assessing Electrochemical Performance

Englisch, 11 Seiten, Release 2011

This document provides tests that record changes in surface insulation resistance (SIR) on a representative sample of a printed circuit assembly. It quantifies any deleterious effects that might arise from solder flux or other process residues left on external surfaces after soldering, which can cause unwanted electrochemical reactions that grossly affect reliability. It uses test vehicles that are intended to be representative of the electronic circuits that are in production and is a test yielding both quantitative and qualitative data. This test may be used for process qualification, demonstrating that a proposed manufacturing process or process change can produce hardware with acceptable end-item performance related to cleanliness. This test may also be used for process characterizations, including development of new processes or improvements to an existing process.

Surface Insulation Resistance Handbook

Englisch. 86 pages. Stand: September 2007

Surface Insulation Resistance (SIR) testing is a tool used not only for characterization testing of production processes such as solder masks, soldering flux, and conformal coatings, but also for examining the electrochemical reactions at each stage of the electronic assembly production process. This handbook covers the terminology, theories, test procedures and test vehicles of SIR testing, including temperature-humidity (TH) and temperature-humidity-bias (THB). Discussions on failure modes and troubleshooting are also included. Revision A provides significant expansion on the discussion of available industry test vehicles for SIR as well as test chamber setup. 86 pages. Released August 2007.

Resin Coated Copper Foil for Printed Boards Guideline

Englisch. Stand: November 2007, 19 pages

This guideline covers the requirements for resin coated copper foil intended for use in the formation of high density interconnect surface microvias for printed boards and printed board assemblies.

Included in Manuals M-105, M-107, S-100 & the E- 500 Collection.

Specification for Embedded Passive Device Resistor Materials for Rigid and Multilayer Printed Boards

Englisch. Stand: Mai 2008, 26 Seiten

This document describes materials that can be used for the fabrication of embedded passive resistor devices within the finished printed circuit board substrate. It provides information on general designations and associated characteristics of embedde d passive device (EPD) resistor materials. The document shall be used as a qualification and conformance standard for designers and users when designing or constructing printed circuit boards containing these EPD materials. This document contains mat erial designation, conformance (requirements), qualification (characterization) and quality assurance specifications. This document should be used in conjunction with both the IPC-2200 series design and the IPC-6010 series qualification and performan ce standards.

Included in the IPC-C-105, IPC-C-107 and the IPC-C-1000 Collections.

Qualification and Performance Specification of Permanent, Semi-Permanent and Temporary Legend and/or Marking Ink

Englisch. Stand: Mai 2008, 17 Seiten

The industry's first specification for the evaluation of a legend and/or marking ink material for the determination of acceptability of use in a standard printed board system. IPC-4781 provides coverage for adhesion, material qualification and testin g, resistances to solvents, requirements for resistance to lead-free solders, and electrical requirements.

Included in the IPC-C-105 and the IPC-C-1000 Collections.

Trouble-Shooting Checklist for Wave Soldering Printed Wiring Boards

Veraltet!

This document provides a checklist of causes/recommended corrective action for wave soldering. Not available in electronic format.

General Specification for Encapsulated Discrete Wire Interconnection Boards

This specification establishes the qualification and performance requirements for encapsulated discrete wire interconnection board with wires that terminate in plated holes.

Computer Numerical Control Formatting for Drillers and Routers

Englisch. Stand: August 1985, 6 Seiten

Defines a machine readable input format for Computer Numerical Control (CNC) drilling and routing machine tools used by the printed wiring board industry. The format may be used to transfer drilling and routing information between printed board designers, manufacturers and users or as the output CNC standard from converters that expand higher level design input such as IPC-D-350 data. Provides a common command structure that can assist in the board manufacturing process and is not intended to provide for every possible software enhancement.

Cleaning Methods and Contamination Assessment for Optical Assembly

Englisch. Stand: Januar 2006; 38 Seiten

This standard describes the methods of inspecting and cleaning all optical interfaces so that interconnectivity integrity of the optical signal is maintained. The information provided focuses on techniques and methods to accomplish maximum quality of the interface and describes methods of contamination prevention. The target audience for this standard are Manufacturing Operators, Manufacturing Process Engineers, Quality Engineers.

Classification of Non-IC Electronic Components for Assembly Processes

Englisch. Stand: August 2008, 12 Seiten

J-STD-075 picks up where J-STD-020 left off by providing test methods to classify worst-case thermal process limitations for electronic components. Classification is referenced to common industry wave and reflow solder profiles including lead-free pr ocessing. The classifications represent maximum process sensitivity levels and do not establish rework conditions or recommended processes for an assembler. It outlines a process to classify and label non-semiconductor electronic component+s Process Sensitivity Level (PSL) and Moisture Sensitivity Level (MSL) consistent with the semiconductor industry+s classification levels (J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Devices and J-STD-033, Handling, Packin g, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices). This standard supersedes IPC-9503. Developed by ECA, IPC and JEDEC.